-- date : Tue Feb 20 13:55:50 2001

-- Entity Declaration

ENTITY decoder IS

PORT (

a : in BIT_VECTOR (0 TO 3); -- a

en : in BIT; -- en

ck : in BIT; -- ck

res : in BIT; -- res

vdd : in BIT; -- vdd

vss : in BIT; -- vss

c : out BIT_VECTOR (0 TO 15) -- c

);

END decoder;

-- Architecture Declaration

ARCHITECTURE VST OF decoder IS

COMPONENT n1_y

port (

i : in BIT; -- i

f : out BIT; -- f

vdd : in BIT; -- vdd

vss : in BIT -- vss

);

END COMPONENT;

COMPONENT a4_y

port (

i0 : in BIT; -- i0

i1 : in BIT; -- i1

i2 : in BIT; -- i2

i3 : in BIT; -- i3

t : out BIT; -- t

vdd : in BIT; -- vdd

vss : in BIT -- vss

);

END COMPONENT;

COMPONENT a2_y

port (

i0 : in BIT; -- i0

i1 : in BIT; -- i1

t : out BIT; -- t

vdd : in BIT; -- vdd

vss : in BIT -- vss

);

END COMPONENT;

SIGNAL o_0an0 : BIT; -- o_0an0

SIGNAL o_10an0 : BIT; -- o_10an0

SIGNAL o_11an0 : BIT; -- o_11an0

SIGNAL o_12an0 : BIT; -- o_12an0

SIGNAL o_13an0 : BIT; -- o_13an0

SIGNAL o_14an0 : BIT; -- o_14an0

SIGNAL o_15an0 : BIT; -- o_15an0

SIGNAL o_1an0 : BIT; -- o_1an0

SIGNAL o_2an0 : BIT; -- o_2an0

SIGNAL o_3an0 : BIT; -- o_3an0

SIGNAL o_4an0 : BIT; -- o_4an0

SIGNAL o_5an0 : BIT; -- o_5an0

SIGNAL o_6an0 : BIT; -- o_6an0

SIGNAL o_7an0 : BIT; -- o_7an0

SIGNAL o_8an0 : BIT; -- o_8an0

SIGNAL o_9an0 : BIT; -- o_9an0

SIGNAL o_inv0 : BIT; -- o_inv0

SIGNAL o_inv1 : BIT; -- o_inv1

SIGNAL o_inv2 : BIT; -- o_inv2

SIGNAL o_inv3 : BIT; -- o_inv3

BEGIN

inv0 : n1_y

PORT MAP (

vss => vss,

vdd => vdd,

f => o_inv0,

i => a(0));

inv1 : n1_y

PORT MAP (

vss => vss,

vdd => vdd,

f => o_inv1,

i => a(1));

inv2 : n1_y

PORT MAP (

vss => vss,

vdd => vdd,

f => o_inv2,

i => a(2));

inv3 : n1_y

PORT MAP (

vss => vss,

vdd => vdd,

f => o_inv3,

i => a(3));

noname0an0 : a4_y

PORT MAP (

vss => vss,

vdd => vdd,

t => o_0an0,

i3 => o_inv0,

i2 => o_inv1,

i1 => o_inv2,

i0 => o_inv3);

noname0an1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => c(0),

i1 => o_0an0,

i0 => en);

noname1an0 : a4_y

PORT MAP (

vss => vss,

vdd => vdd,

t => o_1an0,

i3 => a(0),

i2 => o_inv1,

i1 => o_inv2,

i0 => o_inv3);

noname1an1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => c(1),

i1 => o_1an0,

i0 => en);

noname2an0 : a4_y

PORT MAP (

vss => vss,

vdd => vdd,

t => o_2an0,

i3 => o_inv0,

i2 => a(1),

i1 => o_inv2,

i0 => o_inv3);

noname2an1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => c(2),

i1 => o_2an0,

i0 => en);

noname3an0 : a4_y

PORT MAP (

vss => vss,

vdd => vdd,

t => o_3an0,

i3 => a(0),

i2 => a(1),

i1 => o_inv2,

i0 => o_inv3);

noname3an1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => c(3),

i1 => o_3an0,

i0 => en);

noname4an0 : a4_y

PORT MAP (

vss => vss,

vdd => vdd,

t => o_4an0,

i3 => o_inv0,

i2 => o_inv1,

i1 => a(2),

i0 => o_inv3);

noname4an1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => c(4),

i1 => o_4an0,

i0 => en);

noname5an0 : a4_y

PORT MAP (

vss => vss,

vdd => vdd,

t => o_5an0,

i3 => a(0),

i2 => o_inv1,

i1 => a(2),

i0 => o_inv3);

noname5an1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => c(5),

i1 => o_5an0,

i0 => en);

noname6an0 : a4_y

PORT MAP (

vss => vss,

vdd => vdd,

t => o_6an0,

i3 => o_inv0,

i2 => a(1),

i1 => a(2),

i0 => o_inv3);

noname6an1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => c(6),

i1 => o_6an0,

i0 => en);

noname7an0 : a4_y

PORT MAP (

vss => vss,

vdd => vdd,

t => o_7an0,

i3 => a(0),

i2 => a(1),

i1 => a(2),

i0 => o_inv3);

noname7an1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => c(7),

i1 => o_7an0,

i0 => en);

noname8an0 : a4_y

PORT MAP (

vss => vss,

vdd => vdd,

t => o_8an0,

i3 => o_inv0,

i2 => o_inv1,

i1 => o_inv2,

i0 => a(3));

noname8an1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => c(8),

i1 => o_8an0,

i0 => en);

noname9an0 : a4_y

PORT MAP (

vss => vss,

vdd => vdd,

t => o_9an0,

i3 => a(0),

i2 => o_inv1,

i1 => o_inv2,

i0 => a(3));

noname9an1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => c(9),

i1 => o_9an0,

i0 => en);

noname10an0 : a4_y

PORT MAP (

vss => vss,

vdd => vdd,

t => o_10an0,

i3 => o_inv0,

i2 => a(1),

i1 => o_inv2,

i0 => a(3));

noname10an1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => c(10),

i1 => o_10an0,

i0 => en);

noname11an0 : a4_y

PORT MAP (

vss => vss,

vdd => vdd,

t => o_11an0,

i3 => a(0),

i2 => a(1),

i1 => o_inv2,

i0 => a(3));

noname11an1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => c(11),

i1 => o_11an0,

i0 => en);

noname12an0 : a4_y

PORT MAP (

vss => vss,

vdd => vdd,

t => o_12an0,

i3 => o_inv0,

i2 => o_inv1,

i1 => a(2),

i0 => a(3));

noname12an1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => c(12),

i1 => o_12an0,

i0 => en);

noname13an0 : a4_y

PORT MAP (

vss => vss,

vdd => vdd,

t => o_13an0,

i3 => a(0),

i2 => o_inv1,

i1 => a(2),

i0 => a(3));

noname13an1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => c(13),

i1 => o_13an0,

i0 => en);

noname14an0 : a4_y

PORT MAP (

vss => vss,

vdd => vdd,

t => o_14an0,

i3 => o_inv0,

i2 => a(1),

i1 => a(2),

i0 => a(3));

noname14an1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => c(14),

i1 => o_14an0,

i0 => en);

noname15an0 : a4_y

PORT MAP (

vss => vss,

vdd => vdd,

t => o_15an0,

i3 => a(0),

i2 => a(1),

i1 => a(2),

i0 => a(3));

noname15an1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => c(15),

i1 => o_15an0,

i0 => en);

end VST;