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-- VHDL structural description generated from `mc`
-- date : Tue Feb 20 21:19:15 2001
-- Entity Declaration
ENTITY mc IS
PORT (
x : in BIT; -- x
res : in BIT; -- res
rowsel : in BIT; -- rowsel
wren : in BIT; -- wren
y : out BIT; -- y
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END mc;
-- Architecture Declaration
ARCHITECTURE VST OF mc IS
COMPONENT a2_y
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
t : out BIT; -- t
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT dffres
port (
input : in BIT; -- input
clk : in BIT; -- clk
reset : in BIT; -- reset
output : out BIT; -- output
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT p1_y
port (
i : in BIT; -- i
t : out BIT; -- t
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
SIGNAL c : BIT; -- c
SIGNAL q : BIT; -- q
BEGIN
and1 : a2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => c,
i1 => wren,
i0 => rowsel);
dff : dffres
PORT MAP (
vss => vss,
vdd => vdd,
output => q,
reset => res,
clk => c,
input => x);
buf : p1_y
PORT MAP (
vss => vss,
vdd => vdd,
t => y,
i => q);
end VST;
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