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Introduction

Description

PCI bridge is a member of a family of open source cores. It is a bus bridge device, which enables access to PCI bus to other WISHBONE SoC bus compatible cores. Both sides of bridge can operate at totaly independent clock frequencies. Performance features include 32-bit bus interfaces on both sides, high level of performance and flexibility like burst data transfers, memory access optimizing command usage etc. For detailed information refer to related links.

Purpose of the PCI bridge project

FIRST: All commercial PCI soft cores, that we noticed, are PCI interfaces. They have different backend interfaces. A system designer using PCI interface for some application must also be avare of the PCI protocol. With a PCI bridge a designer considers only the system bus (WISHBONE SoC bus) and can easily focus to his application. (It is true, that PCI interfaces occupy less space) SECOND: We believe that the PCI bridge will be better tested and more imroved because it is an open source PCI bridge core.

What help do we need?

There will be testench prepared soon. Fist it will support MEMORY and CONFIG commands. Some testcases will be written, but there are so many different possibilities, that every help will be needed. Please contact Miha or Tadej.