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Re: [bluetooth] RF solution

To: [email protected]
Subject: Re: [bluetooth] RF solution
From: Puloma Mukherjee <[email protected]>
Date: Mon, 12 May 2003 12:01:33 -0400 (EDT)
In-Reply-To: <[email protected]>
Reply-To: [email protected]
Sender: [email protected]

Hello All,
This is the entire code for CRC,HEC and FEC tested against the sample
datat given in the specification.1/3 FEC has not been implemented yet.
I would like to know if this is synthesisable.I understand Jamil said he
will try and synthesise our codes.Jamil,Please let me know what changes
are to be made to make it synthesisable.

Regards,
Puloma

module FEC(clk,bitsample,blockenable,mode,Din1,Din2,Dout);

input clk;
input bitsample;
input blockenable;
input Din1,Din2;
input [0:1] mode;
output [0:4] Dout;
reg [0:4] lfsr;
reg [0:4] Dout;
reg temp;
reg inputbit;
integer check;
always@(blockenable)
begin
lfsr=5'b00000;
check=0;
end

always @(posedge clk)

begin  
  #1;
  inputbit=bitsample;
  $display($time,"bitsample received:%b",inputbit);
  //$display($time,"Ide this loop blockenable:%b,EOP=%b,Din1=%b",blockenable,EOP,Din1);
 if (blockenable==1'b1 && mode==2'b00  && Din1==1'b1)
     
    begin
      temp=lfsr[0]^inputbit;
      lfsr[0]<=lfsr[1]^temp;
      lfsr[1]<=lfsr[2];
      lfsr[2]<=lfsr[3]^temp;
      lfsr[3]<=lfsr[4];
      lfsr[4]<=temp;
      Dout=lfsr;
      $display("In this Iteration are %b ",Dout);
             
     end
 
             
     
end

endmodule

module CRC(clk,Initvalue,bitsample,blockenable,EOP,Din1,Din2,crcmatch,Dout);

input clk;
input [0:15] Initvalue;
input EOP;
input bitsample;
input blockenable;
output crcmatch;
input Din1,Din2;
output [0:15] Dout;
reg [0:15] Initialvalue;
reg [0:15] Dout;
reg temp;
reg inputbit;
integer check;
always@(Initvalue)
begin
check=check+1;
Initialvalue=Initvalue;
$display($time,"Check is %d",check);
$display($time,"Initial Value is %b",Initialvalue);
end

always @(posedge clk)

begin  
  #1;
  inputbit=bitsample;
  $display($time,"bitsample received:%b",inputbit);
  $display($time,"Inside this loop blockenable:%b,EOP=%b,Din1=%b",blockenable,EOP,Din1);
 if (blockenable==1'b1 && EOP==0 && Din1==1'b1)
     
    begin
      temp=Initialvalue[15]^inputbit;
      Initialvalue[15]<=Initialvalue[14];
      Initialvalue[14]<=Initialvalue[13];
      Initialvalue[13]<=Initialvalue[12];
      Initialvalue[12]<=Initialvalue[11]^temp;
      Initialvalue[11]<=Initialvalue[10];
      Initialvalue[10]<=Initialvalue[9];
      Initialvalue[9]<=Initialvalue[8];
      Initialvalue[8]<=Initialvalue[7];
      Initialvalue[7]<=Initialvalue[6];
      Initialvalue[6]<=Initialvalue[5];
      Initialvalue[5]<=Initialvalue[4]^temp;
      Initialvalue[4]<=Initialvalue[3];
      Initialvalue[3]<=Initialvalue[2];
      Initialvalue[2]<=Initialvalue[1];
      Initialvalue[1]<=Initialvalue[0];
      Initialvalue[0]<=temp;
      Dout=Initialvalue;
      $display("In this Iteration are %b ",Dout);
             
     end
end

endmodule

module HEC(clk,Initvalue,bitsample,blockenable,EOP,Din1,Din2,Dout);

input clk;
input [0:7] Initvalue;
input EOP;
input bitsample;
input blockenable;
input Din1,Din2;
output [0:7] Dout;
reg [0:7] Initialvalue;
reg [0:7] Dout;
reg temp;
reg inputbit;
integer check;
always@(Initvalue)
begin
check=check+1;
Initialvalue=Initvalue;
$display($time,"Check is %d",check);
$display($time,"Initial Value is %b",Initialvalue);
end

always @(posedge clk)

begin  
  #1;
  inputbit=bitsample;
  $display($time,"bitsample received:%b",inputbit);
  $display($time,"Inside this loop blockenable:%b,EOP=%b,Din1=%b",blockenable,EOP,Din1);
 if (blockenable==1'b1 && EOP==0 && Din1==1'b1)
     
    begin
      temp=Initialvalue[7]^inputbit;
      Initialvalue[7]<=Initialvalue[6]^temp;
      Initialvalue[6]<=Initialvalue[5];
      Initialvalue[5]<=Initialvalue[4]^temp;
      Initialvalue[4]<=Initialvalue[3];
      Initialvalue[3]<=Initialvalue[2];
      Initialvalue[2]<=Initialvalue[1]^temp;
      Initialvalue[1]<=Initialvalue[0]^temp;
      Initialvalue[0]<=temp;
      Dout=Initialvalue;
      $display("In this Iteration are %b ",Dout);
             
     end
end

endmodule
//Make changes from here //

module Datapath(clk,HECInitvalue,HECBlockEnable,HECBitSample,HECEOP,HECDin1,HECDin2,HECDout,CRCInitvalue,CRCBlockEnable,CRCBitSample,CRCEOP,CRCDin1,CRCDin2,CRCMatch,CRCDout,FECBlockEnable,FECBitSample,FECmode,FECDin1,FECDin2,FECDout);

input clk;
input [0:4] FECDout;
output FECBlockEnable;
output FECBitSample; 
output [0:1] FECmode;
output FECDin1;
output FECDin2;
input [0:15]CRCDout;
input CRCMatch;
output[0:15] CRCInitvalue;
output CRCBlockEnable;
output CRCBitSample; 
output CRCEOP;
output CRCDin1;
output CRCDin2;
input [0:7] HECDout;
output[0:7] HECInitvalue;
output HECBlockEnable;
output HECBitSample; 
output HECEOP;
output HECDin1;
output HECDin2;
reg CRCBlockEnable;
reg CRCBitSample;
reg CRCEOP;
reg CRCDin1;
reg CRCDin2;
reg [0:47] CRCinputdata;
reg [0:63] CRCfinaloutput;
reg [0:15] CRCInitvalue;
integer CRCcount;

reg FECBlockEnable;
reg FECBitSample;
reg [0:1] FECmode;
reg FECDin1;
reg FECDin2;
reg [0:9]FECinputdata;
reg [0:4]FECfinaloutput;
integer FECcount;


reg HECBlockEnable;
reg HECBitSample;
reg HECEOP;
reg HECDin1;
reg HECDin2;
reg [0:9]HECinputdata;
reg [0:7]HEClfsr;
reg [0:17]HECfinaloutput;
reg [0:7] HECInitvalue;
integer HECcount;
initial
begin
 
  HECfinaloutput[0:17]=18'b000000000000000000;
  HECinputdata=10'b1100010010; // For DM1 substitute 1101100010
  HECInitvalue[0:7]=8'b11100010;
  $display ($time,"Initial Value:%b",HECInitvalue);
  HECDin1=1'b1;
  HECDin2=0;
  HECBlockEnable=1'b1;
  HECEOP=1'b0;
  HECcount<=0;
end

initial
begin
 
  FECfinaloutput[0:4]=5'b00000;
  FECinputdata=10'b000000010;
  FECDin1=1'b1;
  FECDin2=0;
  FECBlockEnable=1'b1;
  FECmode=2'b01;
  FECcount<=0;
end
initial
begin
 
  CRCfinaloutput[0:15]=16'b0000000000000000;
  CRCinputdata=48'b011101001000000001000000110000000010000010100000;
  CRCInitvalue[0:15]=16'b1110001000000000;
  $display ($time,"Initial Value:%b",CRCInitvalue);
  CRCDin1=1'b1;
  CRCDin2=0;
  CRCBlockEnable=1'b1;
  CRCEOP=1'b0;
  CRCcount<=0;
end


always@(posedge clk)

begin

if (FECcount>10)
begin
FECBlockEnable=1'b0; 
FECfinaloutput=FECDout;
//$display ($time,"Output data = %b\n",FECfinaloutput);

end 

else

begin
FECBlockEnable=1'b1;
FECBitSample=FECinputdata[FECcount];
//$display($time,"FECBit Sample is  %b",FECBitSample);
FECcount=FECcount+1; 

end

end


always@(posedge clk)
begin

if(HECcount>10) 

begin
HECBlockEnable = 1'b0;
HECfinaloutput[0:9]=HECinputdata;
HECfinaloutput[10:17]=HECDout;
$display ($time,"Complete Header with HEC = %b\n",HECfinaloutput);

end 

else

begin

HECBitSample=HECinputdata[HECcount];
//$display($time,"HECBit Sample is  %b",HECBitSample);
HECcount=HECcount+1; 
HECBlockEnable=1'b1;
end

end


//initial

// begin
// $monitor($time,"Output data = %b\n",finaloutput);
// end
always@(posedge clk)

begin

if (CRCcount>48)
begin
CRCEOP=1;
CRCfinaloutput[0:47]=CRCinputdata;    
CRCfinaloutput[48:63]=CRCDout;
$display ($time,"Complete Payload including Header and CRC = %b\n",CRCfinaloutput);
$display ($time,"Complete Header with HEC = %b\n",HECfinaloutput);
$finish;
end 

else

begin

CRCBitSample=CRCinputdata[CRCcount];
//$display($time,"CRCBit Sample is  %b",CRCBitSample);
CRCcount=CRCcount+1; 

end

end



endmodule



module Baseband_Controller;

wire CRCbitsamplew,CRCblockenablew,CRCEOPw,CRCDin1w,CRCDin2w,crcmatchw;
wire [0:15] CRC_INITIAL_VALUEw,CRCDoutw;
wire HECbitsamplew,HECblockenablew,HECEOPw,HECDin1w,HECDin2w;
wire [0:7] HEC_INITIAL_VALUEw,HECDoutw;
wire FECbitsamplew,FECblockenablew,FECDin1w,FECDin2w;
wire [0:1] FECmodew;
wire [0:4] FECDoutw;
reg clk;
Datapath sys_ctrl (clk,HEC_INITIAL_VALUEw,HECblockenablew,HECbitsamplew,HECEOPw,HECDin1w,HECDin2w,HECDoutw,CRC_INITIAL_VALUEw,CRCblockenablew,CRCbitsamplew,CRCEOPw,CRCDin1w,CRCDin2w,crcmatchw,CRCDoutw,FECblockenablew,FECbitsamplew,FECmodew,FECDin1w,FECDin2w,FECDoutw);
CRC crclf (clk,CRC_INITIAL_VALUEw,CRCbitsamplew,CRCblockenablew,CRCEOPw,CRCDin1w,CRCDin2w,crcmatchw,CRCDoutw);
HEC heclf (clk,HEC_INITIAL_VALUEw,HECbitsamplew,HECblockenablew,HECEOPw,HECDin1w,HECDin2w,HECDoutw);
FEC feclf (clk,FECbitsamplew,FECblockenablew,FECmodew,FECDin1w,FECDin2w,FECDoutw);



initial
begin
clk=1'b0;
end

always
begin
#2 clk = ~clk;
$display("Clk is %b",clk);
end

//initial

//begin
//#100;
//$finish;
//end


endmodule

References:
- [bluetooth] RF solution
  - From: Mohammad Omara <[email protected]>

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