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Re: [bluetooth] General comments about the codes




Hi,
Please find my answers below.

On 5/23/2003, "Puloma Mukherjee" <[email protected]> wrote:

>alright I have made a note of that...but I dont understand what you mean
>by
>using defined constants...?

try to check the VHDL file at
http://www.opencores.org/cvsweb.shtml/bluetooth_bb/rtl/vhdl/bb_lib/constants_pkg.vhd
May be we I will create a new one for verilog this weekend unless someone
else can do it before that.
If you think that there should be another constants let me know. The whole
idea about these constants is to make a uniform code between all of us.

I would appreciate it if you can explain.
>After making these changes within the next one week and  i will send it
>directly to your account if
>that
>is ok.

Yes please do send them to me to my email and please try to make sure that
you make proper use of the display function since it can not be synthesized
you have to put it between fi define dsimulation statments

Also I will be working on access code generator/ corelator block in
>the following week,please let me know if someone is already doing it.

Try to check my old bluetooth module at opencores
http://www.opencores.org/cvsweb.shtml/bluetooth

This
>week it doesnt look like it will be possible,but
>next week for sure.
>Also, if it is not a problem for people on this list to reveal,I want to
>know where you all are working,for what companies?

I am working for Siemens Palestine as an FPGA design engineer. Anyhow my work
here is not related to siemens I am doing it on my free time at home.

>Thankyou,
>Regards,
>Puloma
>
>On Thu, 22 May 2003, Jamil Khatib wrote:
>
>>
>> Hi,
>> I made a quick review over the files I got on the mailing list (FH
selector,
>> CRC, HEC & FEC) I would like from all of you to try to put teh display
>> function within an if statments that are executed when simulation variable
is
>> defined so that I do not need to comment and uncomment them whenever I
want
>> to synthesize the code.
>> Another comment that I highly recommend you using defined constants such
>> those I defined in the contansts package for VHDL code which is available
in
>> the CVS.
>>
>> Could you please update your files according to these two comments while I
go
>> into deep review. Anyhow I can not synthesize the files easly without
>> following the first note.
>>
>> Regards,
>> Jamil Khatib
>>
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>
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