[oc] About VHDL

[demon_zhu <demon_zhu@sina.com>]

Hi all:
   Does VHDL have same functions/tasks as '$dumpfile, $dumpvars' 
in verilog?
  

Regards

______________________________________

===================================================================
�����������15M�շ����� �Ͻ��ж��� (http://vip.sina.com/sol_mail/promotion/pro_men.html)
���˶����г���һԪͶ�룬ʮ�־�ϲ���ٷ����� (http://classad.sina.com.cn/2shou/)
�������ֻ�ͼƬ�����׶�������������ѡ��ÿ�춼�и��� (http://sms.sina.com.cn/cgi-bin/sms/smspic.cgi)
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml