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RE: [oc] hexadecimal
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.std_logic_textio.all;
package log is
file data_file_handler : text open write_mode is "log.txt";
procedure print_vs(arg: string;address: std_logic_vector;data:
std_logic_vector);
end log;
package body log is
----------------------------------------------------------------------------
--------
procedure print_vs(arg: string;
address: std_logic_vector;
data: std_logic_vector) is
variable tranx : line;
variable l : line;
--********************************************************************
begin
--print to output file
write(l,now, justified=>right,field =>10, unit=> ns );
write(l,string'(" "));
hwrite(l,address,justified=>left);
write(l,string'(" "));
hwrite(l,data);
write(l,arg);
writeline(data_file_handler,l);
write(tranx, now, justified=>right,field =>10, unit=> ns );
write(tranx, string'(" "));
hwrite(tranx,address,justified=>left);
write(tranx, string'(" "));
hwrite(tranx,data);
write(tranx,arg);
writeline(output,tranx);
end print_vs;
end;
-----Original Message-----
From: [email protected]@ROCKWELLCOLLINS On Behalf Of
demon_zhu <[email protected]>
Sent: Tuesday, February 11, 2003 9:11 PM
To: [email protected]
Subject: [oc] hexadecimal
Hello everyone,
I used to code with VERILOG, but now i must
use VHDL.
Could you tell me how to display a integer value with
hexadecimal format? Are there fuctions/procedures in being?
In VERILOG i can do it by $display( "...%x....", a_int);
Thanks
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