[cvs-checkins] uart16550/rtl/verilog uart_fifo.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	mohor	01/08/24 10:48:11

Modified files:
	rtl/verilog    : uart_fifo.v 

Log message:
	FIFO was not cleared after the data was read bug fixed.

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