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[cvs-checkins] ethernet/rtl/verilog eth_wishbone.v

To: [email protected]
Subject: [cvs-checkins] ethernet/rtl/verilog eth_wishbone.v
From: OpenCores CVS Agent <[email protected]>
Date: Wed, 4 Sep 2002 17:47:58 -0100
Sender: [email protected]

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/09/04 17:47:58

Modified files:
	rtl/verilog    : eth_wishbone.v 

Log message:
	Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
	changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
	was not used OK.
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