-----Original Message-----
From: [email protected] [mailto:[email protected]]On Behalf Of [email protected]
Sent: 08. avgust 2001 4:32
To: [email protected]
Subject: RE: [ethmac] wishbone dma bug
I don't know whether it is helpful.
The always block is from wishbonedma.v
only one if statement can exist in a always block or it can not be synthesized.
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
if(WB_RST_I)
TxValidBytesLatched <=#Tp 2'h0;
else
if(TxEndFrm_wb & ~TxEndFrm_wbLatched)
TxValidBytesLatched <=#Tp TxValidBytes;
else //"else" is added /*yxzhou*/
if (TxRestartPulse | TxDonePulse | TxAbortPulse)
TxValidBytesLatched <=#Tp 2'h0;
����Ӧ �� [email protected]
������: [email protected]
�ռ���: "Igor Mohor (uni-mb)" <[email protected]>
���: [email protected]
����: RE: [ethmac] wishbone dma bug
> Hi,
>
> You didn't say much what happened. Perhaps you forgot to set the include
> directory in
> the ModelSim. Tell me more what seems to be the problem (error messages,
> e
what do you mean with include director ModelSim, is
that work library? the other modules are ok. only the wishbone.
thank youe
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