Re: [usb] Re: usb-digest V1 #80

[he.yuzhang@mail.zte.com.cn]

----- Original Message ----- 
From: "John Paul Aguiling" <johnpaolo_a@e... > 
To: usb@o...  
Date: Mon, 24 Sep 2001 20:14:42 +0800 
Subject: [usb] Re: usb-digest V1 #80 

> 
> 
> 
>     Hello everybody... I am just new here in the society. I was 
> wondering if people subscribe here are professionals. As I read 
> different kind of newsletter I received in USB. I was amazed to the 
> different stories and that I can relate to them. I'm just a student 
> here in the Philippines but I was not involve to such organizations 
> like this. I would like to have a brief knowledge about USB some 
> are designing WOW! How impressive. I am designing too as a 
> graduating student but its about PIC programming, which involve 
> interface to PC. Anyway to much for that, I am interested much more 
> in USB because I thirst knowledge for this device and I barely know 
> these things. Thank you very much for different information, I hope 
> there is an illustrations involve, so I can also do it practically 
> at home. 
> 
> usb@o...  wrote: 
> 
> > 
> > usb@o... 	 usb-digest V1 #80 
> > 
> > 
> 
> >------------------------------------------------------------------
---- 
> >From: "Luis J. Perez" <luis.perez@d... > 
> >Date: Wed, 19 Sep 2001 12:11:35 +0200 
> >Subject: Re: [usb] question about the DLL in the UTMI 
> > 
> >Jiang daosan wrote: 
> >> 
> >>  Hi, Luis: 
> >> 
> >>      Thank you so much for your answer.  However, I think 
> there maybe something 
> >> to talk about more, As you written: 
> >> >To design a HS PLL you need an external clock of 480x4 
> MHz (at least, I 
> >> >think) to obtain the data signal synchronized with the 
> internally 
> >> >extracted 480 MHz clock. 
> >> I was wonder that there is some mistake? As the external 
> clock of 480x4 MHz is 
> >> so high, it may be impossibe in practice. I saw the needed 
> external clock in 
> >> Phlips ISP1501 is 12MHz. In my opinion, the internal local 
> 480MHz clock is 
> >> produced by the Clock Multiplier with the external 12MHz 
> Clock in the UTM, 
> >> And then it was made some Phase delay by the HS DLL to 
> synchronized to the clock of 
> >> the incoming data. That delayed Clock is the exacted 
> clock. Am I right ? 
> >> 
> > 
> >Yes, sorry, I was thinking on my design... 
> > 
> >The delayed clock you are referring is the extracted clock (480 
> MHz 
> >one). But, how to 
> >design in HDL a Digital PLL for HS? I don't know another way of 
> >syncronizing both clocks (internal and the incoming data one) 
> than 
> >sampling the incoming data with a quicker clock. Any other 
> idea? 
> > 
> > 
> 
>=====================================================
=== 
> >Luis Jose Perez Lafuente      	luis.perez@d...  
> >Design Engineer 
> >Digital Design Department 
> > 
> >Design of Systems on Silicon  	http://www.ds2.es 
> >Av. Charles Robert Darwin, 2  	Phone.  +34-96-136 60 04 
> >Parc Tecnologic	              	                Ext. 152 
> >46980 Paterna (VALENCIA)      	FAX     +34-96-136 62 50 
> >SPAIN 
> 
>=====================================================
=== 
> > 
> > 
> 
> >------------------------------------------------------------------
---- 
> >From: Rudolf Usselmann <rudi@a... > 
> >Date: Wed, 19 Sep 2001 20:11:02 +0700 
> >Subject: Re: [usb] question about the DLL in the UTMI 
> > 
> >On Wednesday 19 September 2001 17:11, you wrote: 
> >> Jiang daosan wrote: 
> >> >  Hi, Luis: 
> >> > 
> >> >      Thank you so much for your answer.  However, I 
> think there maybe 
> >> > something 
> >> > 
> >> > to talk about more, As you written: 
> >> > >To design a HS PLL you need an external clock of 
> 480x4 MHz (at least, 
> >> > > I think) to obtain the data signal synchronized 
> with the internally 
> >> > > extracted 480 MHz clock. 
> >> > 
> >> > I was wonder that there is some mistake? As the 
> external clock of 480x4 
> >> > MHz is so high, it may be impossibe in practice. I 
> saw the needed 
> >> > external clock in Phlips ISP1501 is 12MHz. In my 
> opinion, the internal 
> >> > local 480MHz clock is produced by the Clock 
> Multiplier with the 
> >> > external 12MHz Clock in the UTM, And then it was made 
> some Phase delay 
> >> > by the HS DLL to synchronized to the clock of the 
> incoming data. That 
> >> > delayed Clock is the exacted clock. Am I right ? 
> >> 
> >> Yes, sorry, I was thinking on my design... 
> >> 
> >> The delayed clock you are referring is the extracted clock 
> (480 MHz 
> >> one). But, how to 
> >> design in HDL a Digital PLL for HS? I don't know another 
> way of 
> >> syncronizing both clocks (internal and the incoming data 
> one) than 
> >> sampling the incoming data with a quicker clock. Any other 
> idea? 
> >> 
> >> 
> >> 
======================================================
== 
> >> Luis Jose Perez Lafuente      	luis.perez@d...  
> > 
> >High Speed USB uses a bit clock of 480 Mhz, Full Speed of 12 
> Mhz. 
> > 
> >A HS PHY uses a analog PLL to recover the 480 Mhz clock. You do 
> not 
> >need a 4x480Mhz clock (unless you do want to design a Digital 
> LL, in which 
> >case you would need at least 4x oversampling). 
> > 
> >rudi 
> > 
> > 
> 
> >------------------------------------------------------------------
---- 
> >From: Rudolf Usselmann <rudi@a... > 
> >Date: Mon, 24 Sep 2001 08:26:02 +0700 
> >Subject: [usb] USB Core Updated 
> > 
> >I have changed the reset in the USB core to be active high and 
> async. 
> > 
> >Latest and greatest is in the CVS ... 
> > 
> >rudi 
> > 
> > 
> 
> >------------------------------------------------------------------
---- 
> >End of usb-digest V1 #80 
> >- 
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> > 
> > 
> 
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