Re: [usb] timing diagram request...

[utada23@hotmail.com]

thanks a lot for the info!...

----- Original Message ----- 
From: Rudolf Usselmann <rudi@a... > 
To: usb@o...  
Date: Mon, 18 Feb 2002 21:10:55 +0700 
Subject: Re: [usb] timing diagram request... 

> 
> 
> 
> On Monday 18 February 2002 07:05 pm, you wrote: 
> > hi!...Its me again...to anybody who has seen the usb core...I 
> have 
> > questions regarding the endpoints and how the SSRAM is divided 
> among 
> > them...does memory mapping applies to this?... or the whole 
> SSRAM is 
> > accessible to all endpoints?...or each endpoints has its own 
> > SSRAM?...I'll be waiting for your responds...thanks! 
> 
> The entire SSRAM is shared between all endpoints. It is up to the 
> micro controller to divide the memory between the endpoints. 
> 
> > > Mr Rudolf Usselmann, 
> > > 
> > > Hello!...I'm new here...and I'm currently studying your 
> usb 
> > > core...good 
> > > job!...I hope you don't mind if I request a timing 
> diagram of the 
> > > wishbone IF...particularly the DMA transfer...this will 
> be greatly 
> > > appreciated! 
> 
> Everything that is available is in the USB specification. 
> 
> > > regards, 
> > > utada 
> 
> 
> regards, 
> rudi 
> 
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