[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [oc] constraints while programming in VHDL
>>>>> "ritika" == ritika dua <[email protected]> writes:
ritika> sir, i want to know how we can use delays in the vhdl code, as
ritika> the delays can't be synthesized .
Count clock cycles for delay, or go external and use a delay line.
Any other solution is problematic.
Bye
--
Uwe Bonnes [email protected]
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml