Mail Index

• Thread Index

• [oc] Transfering data via I2C Master Core
  • From: "matija habek" <[email protected]>
• [oc] Clock frequency generator
  • From: [email protected]
• [oc] Fwd: your software
  • From: "Ariadne Hunt" <[email protected]>
• Re: [oc] SNR Calculation using CADENCE SpectreS tool
  • From: [email protected]
• [oc] LogiCore 1024 point FFT issue ?
  • From: "Saumil Merchant" <[email protected]>
• Re: [oc] Uart 16550 Wishbone to Avalon
  • From: "Robinluo\(Cytech FAE\)" <[email protected]>
• [oc] Uart 16550 Wishbone to Avalon
  • From: "Jared Francom" <[email protected]>
• [oc] programming xc95144 with Parallel cable IV
  • From: "Haytham Azmi" <[email protected]>
• RE: [oc] vhdl question
  • From: [email protected] (spyros)
• Re: [oc] Re: code for usart
  • From: [email protected]
• Re: [oc] vhdl question
  • From: Atul Ware <[email protected]>
• RE: [oc] numeric PIN or PAD number
  • From: "Jerrold Wen" <[email protected]>
• Odp: [oc] vhdl question
  • From: "Jerzy G" <[email protected]>
• Re: [oc] vhdl question
  • From: "Henchinski" <[email protected]>
• Re: [oc] vhdl question
  • From: spyros <[email protected]>
• [oc] vhdl question
  • From: "Saumil Merchant" <[email protected]>
• Re: [oc] interfacing 16Mhz and I Mhz clock registers
  • From: John Sheahan <[email protected]>
• Re: [oc] interfacing 16Mhz and I Mhz clock registers
  • From: "Jim Dempsey" <[email protected]>
• Re: [oc] interfacing 16Mhz and I Mhz clock registers
  • From: "H. Peter Anvin" <[email protected]>
• Re: [oc] interfacing 16Mhz and I Mhz clock registers
  • From: John Sheahan <[email protected]>
• Re: [oc] interfacing 16Mhz and I Mhz clock registers
  • From: Umair Farooq Siddiqi <[email protected]>
• RE: [oc] verilog CAN core implementation issues
  • From: "Igor Mohor\(opencores\)" <[email protected]>
• Re: [oc] interfacing 16Mhz and I Mhz clock registers
  • From: John Sheahan <[email protected]>
• [oc] interfacing 16Mhz and I Mhz clock registers
  • From: Umair Farooq Siddiqi <[email protected]>
• Re: [oc] linux xilinx webpack programming
  • From: Uwe Bonnes <[email protected]>
• Re: [oc] linux xilinx webpack programming
  • From: [email protected]
• Re: [oc] VHDL PID Motor Controller
  • From: [email protected]
• [oc] help,TMAX question.
  • From: "Gengbo" <[email protected]>
• Re: [oc] Query abt Switch level modelling in Verilog
  • From: John Sheahan <[email protected]>
• Re: [oc] numeric PIN or PAD number
  • From: Uwe Bonnes <[email protected]>
• Re: [oc] Query abt Switch level modelling in Verilog
  • From: "R. Ramakrishna" <[email protected]>
• [oc] numeric PIN or PAD number
  • From: paul <[email protected]>
• Re: [oc] constraints while programming in VHDL
  • From: John Sheahan <[email protected]>
• Re: [oc] constraints while programming in VHDL
  • From: Uwe Bonnes <[email protected]>
• Re: [oc] constraints while programming in VHDL
  • From: [email protected]
• Re: Re: [oc] 8-PSK
  • From: "henry_xb" <[email protected]>
• Re: [oc] 8-PSK
  • From: "Haytham" <[email protected]>
• [oc] 8-PSK
  • From: [email protected]
• [oc] Swan cum-writer Cores esivunguvungwini
  • From: Shawn Saltzgaber <[email protected]>
• Re: [oc] Query abt Switch level modelling in Verilog
  • From: John Sheahan <[email protected]>
• [oc] =?GB2312?B?s6zWtdeqyMMtLbGxvqm498DgxvPStUhSo6jIy8Gm18rUtL6twO2jqcP7wrw=?=
  • From: =?GB2312?B?zuK2qw==?= <[email protected]>
• [oc] Query abt Switch level modelling in Verilog
  • From: "R. Ramakrishna" <[email protected]>
• Re: [oc] The use of both edge of the clock.
  • From: John Sheahan <[email protected]>
• Re: [oc] The use of both edge of the clock.
  • From: Uwe Bonnes <[email protected]>
• Re: [oc] verilog CAN core implementation issues
  • From: Uwe Bonnes <[email protected]>
• [oc] The use of both edge of the clock.
  • From: <[email protected]>
• [oc] verilog CAN core implementation issues
  • From: [email protected]
• RE: [oc] VHDL Help...
  • From: "Larsen, Henning Engelbrecht" <[email protected]>
• [oc] OpenTech cdroms new release
  • From: Jamil Khatib <[email protected]>
• ReRe: [oc] MP3 Encoder?
  • From: otto otto <[email protected]>
• Re: [oc] MP3 Encoder?
  • From: [email protected]
• Re: [oc] verilog coding standards document
  • From: "R. Ramakrishna" <[email protected]>
• Re: [oc] verilog coding standards document
  • From: Uwe Bonnes <[email protected]>
• Re: [oc] verilog coding standards document
  • From: Marko Mlinar <[email protected]>
• [oc] verilog coding standards document
  • From: "Ana Rita Matias (WITHUS)" <[email protected]>
• Re: [oc] [PATCH] UART receiver bugs
  • From: Jacob Gorban <[email protected]>
• [oc] [PATCH] UART receiver bugs
  • From: Scott Furman <[email protected]>
• Re: [oc] Re: ip help
  • From: Shawn Tan <[email protected]>
• [oc] Re: ip help
  • From: =?gb2312?B?1cXJvbjV?= <[email protected]>
• Re: [oc] VHDL Help...
  • From: Jason Silcox <[email protected]>
• Re: [oc] uart modem outputs
  • From: Jacob Gorban <[email protected]>
• RE: [oc] uart modem outputs
  • From: "Leo Jarillas" <[email protected]>
• Re: [oc] uart modem outputs
  • From: John Sheahan <[email protected]>
• Re: [oc] TMS34010
  • From: Paul Cousoulis <[email protected]>
• [oc] uart modem outputs
  • From: "Leo Jarillas" <[email protected]>
• Re: [oc] core for FFT/IFFT (1024 point)for 802.11a protocol
  • From: [email protected]
• Re: [oc] TMS34010
  • From: Charles Lepple <[email protected]>
• [oc] TMS34010
  • From: Paul Cousoulis <[email protected]>
• Re: [oc] Patents and their applicability
  • From: alex patience <[email protected]>
• Re: [oc] or1200 compilation problem
  • From: "Damjan Lampret" <[email protected]>
• [oc] I thought that this might be interesting.
  • From: Lars Segerlund <[email protected]>
• [oc] or1200 compilation problem
  • From: paul <[email protected]>
• Re: [oc] DMA in ethernet
  • From: "Igor Mohor" <[email protected]>
• Re: [oc] Delay and latency ?
  • From: Joachim Str�mbergson<[email protected]>
• Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
  • From: =?UTF-8?B?Sm9hY2hpbSBTdHLDtm1iZXJnc29u?=<[email protected]>
• Re: [oc] Delay and latency ?
  • From: Marko Mlinar <[email protected]>
• Re: [oc] wishbone performance
  • From: Marko Mlinar <[email protected]>
• [oc] DMA in ethernet
  • From: [email protected]
• [oc] If anyone has a free AMBA AHB to wishbone or AHB master or slave
  • From: [email protected]
• Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
  • From: Tom Hawkins <[email protected]>
• Re: [oc] Newbie question - matricies and vectors for physics
  • From: Tom Hawkins <[email protected]>
• Re: [oc] Delay and latency ?
  • From: John Dalton <[email protected]>
• Re: [oc] 8255 PPI VHDL CODE
  • From: "Robinluo\(Cytech FAE\)" <[email protected]>
• [oc] 8255 PPI VHDL CODE
  • From: [email protected]